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general description the max16922 power-management integrated circuit (pmic) is designed for medium power-level automotive applications and integrates multiple supplies in a small footprint. the device includes one high-voltage step- down converter (out1) and three low-voltage cascad- ed dc-dc converters (out2, out3, out4). out1 and out2 are step-down dc-dc converters, and out3/ out4 are linear regulators. the device also includes a reset output ( reset ) and a high-voltage-compatible enable input (en). the 1.2a output high-efficiency, step-down dc-dc con- verter (out1) operates from a voltage up to 28v contin- uous and is protected from load-dump transients up to 45v. the 600ma output high-efficiency step-down dc- dc converter (out2) runs from a voltage up to 5.5v. the two 300ma ldo linear regulators offer low dropout of only 130mv (typ). the power-good reset output provides voltage monitoring for out1 and out2. out1 and out2 use fast 2.2mhz pwm switching and small external components. the high-voltage converter (out1) enters skip mode automatically under light loads to prevent an overvoltage condition from occur- ring at the output. the low-voltage synchronous dc-dc converter (out2) can operate in forced-pwm mode to prevent any am band interference or high-efficiency auto-pwm mode. the max16922 includes overtemperature shutdown and overcurrent limiting. the device is designed to operate from -40? to +125? ambient temperature. features ? 1.2a high-efficiency 2.2mhz dc-dc converter 3.7v to 28v operating supply voltage 45v load-dump protection output voltage: 3.0v to 5.5v ? 600ma high-efficiency 2.2mhz dc-dc converter 2.7v to 5.5v supply voltage output voltage: 1.0v to 3.9v 180 out-of-phase operation forced-pwm and auto-pwm modes ? ldo linear regulators out3: 1.0v to 4.15v at 300ma out4: 1.0v to 4.15v at 300ma separate inputs for increased efficiency ? enable input ? reset output monitoring on out1 and out2 ? overtemperature and short-circuit protection ? available in 5mm x 5mm x 0.8mm, 20-pin tqfn-ep 4.5mm x 6.5mm, 20-pin tssop-ep max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset ________________________________________________________________ maxim integrated products 1 19-5039; rev 5; 1/12 evaluation kit available ordering information part temp range pin-package max16922atp_ /v+* -40? to +125? 20 tqfn-ep** max16922aup_ /v+* -40? to +125? 20 tssop-ep** * insert the desired suffix letters (from the selector guide) into the blank ??to complete the part number. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. ** ep = exposed pad. typical operating circuit max16922 ep pv1 en 4.7 f 1 f 0.1 f 10 f v pv1 pv3 pwm 4.7 f v out1 out3 gnd1 gnd3 4.7 f v out3 pv4 outs1 4.7 f v out2 v out1 out4 gnd2 20k reset gnd 4.7 f v out4 lsup 4.7 h lx1 v out1 bst pv2 10 f pgnd2 2.2 h lx2 v out2 outs2 4.7 f for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25? under normal conditions, unless otherwise noted.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . pv1, en to gnd .....................................................-0.3v to +45v lx1 to gnd.................................................-0.5v to (pv1 + 0.3v) lx2 to gnd.................................................-0.5v to (pv2 + 0.3v) bst to lx1.............................................................-0.3v to +6.0v pv2, pv3, pv4, outs1, pwm, reset to gnd_....-0.3v to +6.0v outs2 .......................................................-0.3v to (pv2 + 0.3v) out3 .........................................................-0.3v to (pv3 + 0.3v) out4 .........................................................-0.3v to (pv4 + 0.3v) lx1 rms current .................................................................2.0a lx2 rms current .................................................................1.2a pgnd2 to gnd_....................................................-0.3v to +0.3v lsup to gnd............................................................-0.3v to +6v outs_, out_ output short-circuit duration .............continuous continuous power dissipation (t a = +70?) tqfn (derate 31.3 mw/? above +70?) ........................ 2500mw tssop (derate 26.5 mw/? above +70?) ...................... 2122mw esd hb (all pins) ...................................................................?kv esd mm (all pins) ................................................................?00v esd cdm (corner pins) .......................................................?50v esd cdm (other pins)..........................................................?00v operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( ja ) ........... 32?/w junction-to-case thermal resistance ( jc ) ............... 2.7?/w tssop junction-to-ambient thermal resistance ( ja ) ........ 37.7?/w junction-to-case thermal resistance ( jc ) .................. 2?/w parameter symbol conditions min typ max units out1synchronous step-down dc-dc converter (note 3) 3.7 28 supply-voltage range v pv1 operation < 500ms 45 v v uvlo,r pv1 rising 3.7 4.0 pv1 undervoltage lockout v uvlo,f pv1 falling 2.85 3.3 v bst refresh load enable v brle pv1 falling (option enabled) 6.45 v bst refresh load hysteresis 0.65 v lsup regulator voltage v lsup 6v v pv1 28v 4.75 5.0 5.45 v supply current i pv1 en = low 14 a pwm switching frequency f sw internally generated 2.0 2.2 2.4 mhz duty cycle = 20% to 90%; i load = 300ma to 1.2a -3 +3 voltage accuracy v out1 skip mode (note 4) -2 +4 % dmos on-resistance v pv1 = 4v, v bst = 9v, i lx1 = 0.2a 300 700 m current-limit threshold 1.4 1.75 2.1 a soft-start ramp time 2.2 ms
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units maximum output current i out1 (v out1 + 1.0v) v pv1 28v 1.2 a lx1 leakage current v pv1 = 12v, lx1 = gnd or v pv1 ; t a = -40c to +85c 1 a maximum duty cycle dc max 94 % minimum duty cycle dc min f sw = 2.2mhz 20 % outs1 discharge resistance en = low (or optionally en = high and v pv1 < 5.7v) 70 out2synchronous step-down dc-dc converter supply-voltage range v pv2 fully operational 2.7 5.5 v pwm switching frequency f sw internally generated 2.0 2.2 2.4 mhz duty cycle = 20% to 90%; i load = 1ma to 600ma, pwm = high -3 +3 % voltage accuracy v out2 skip mode (note 4) -2 +4 % pmos on-resistance v pv2 = 5.0v, i lx2 = 0.2a 150 250 m nmos on-resistance v pv2 = 5.0v, i lx2 = 0.2a 200 350 m pmos current-limit threshold 0.75 0.9 1.05 a nmos zero-crossing threshold 50 ma soft-start ramp time 1.5 ms maximum output current i out2 v out2 + 0.5v v pv2 5.5v 600 ma lx2 leakage current v pv2 = 6v, lx2 = pgnd2 or v pv2 ; t a = -40c to +85c 1 a duty-cycle range forced-pwm mode only, minimum duty cycle in skip mode is 0% (note 4) 15 100 % outs2 discharge resistance v en = 0v 70 out3ldo regulator input voltage v pv3 1.7 5.5 v voltage accuracy v out3 v out3 + 0.4v v pv3 5.5v, i load = 1ma -2 +2 % load regulation i load = 0 to 300ma -0.2 % dropout voltage v pv3 = 1.8v, i load = 250ma (note 4) 130 320 mv current limit 450 ma power-supply rejection ratio i out3 = 30ma, f = 1khz 57 db shutdown output resistance en = low 1 k out4ldo regulator input voltage v pv4 1.7 5.5 v voltage accuracy v out4 (v out4 + 0.4v) v pv4 5.5v, i load = 1ma -2 +2 % load regulation i load = 0 to 300ma -0.2 % dropout voltage v pv4 = 1.8v, i load = 250ma (note 4) 130 320 mv current limit 450 ma electrical characteristics (continued) (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25? under normal conditions, unless otherwise noted.) (note 2)
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 4 _______________________________________________________________________________________ electrical characteristics (continued) (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25? under normal conditions, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units power-supply rejection ratio i out4 = 30ma, f = 1khz 57 db shutdown output resistance en = low 1 k thermal overload thermal-shutdown temperature (note 4) 150 175 c thermal-shutdown hysteresis 15 c reset out1 ov threshold 110 % reset option 1 (see the selector guide ) 85 90 95 out1 reset threshold reset option 2 (see the selector guide ) 75 80 85 % out2 reset threshold percentage of nominal output 85 90 95 % reset timeout option 1 (see the selector guide ) 14.9 reset timeout period reset timeout option 2 (see the selector guide ) 1.9 ms output-high leakage current 1 a output low level sinking -3ma 0.4 v uv propagation time 28 s en logic input en threshold voltage en rising 1.4 1.8 2.2 v en threshold hysteresis 0.4 v input current v en = 5v 0.5 a pwm logic input input high level pwm rising 1.8 v input low level pwm falling 0.4 v logic-input current 0 v pwm 5.5v 1 a note 2 : all units are 100% production tested at t a = +25?. all temperature limits are guaranteed by design. note 3 : once pvi exceeds undervoltage-lockout rising threshold 4.0v and the device is in regulation. note 4 : guaranteed by design; not product tested.
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset _______________________________________________________________________________________ 5 out1 efficiency vs. load current max16922 toc01 load current (a) efficiency (%) 1.1 1.0 0.8 0.9 0.3 0.4 0.5 0.6 0.7 0.2 10 20 30 40 50 60 70 80 90 100 pv1 = 18v pv1 = 13.5v pv1 = 8v 0 0.1 1.2 out1 efficiency vs. load current max16922 toc02 load current (a) efficiency (%) 1.1 1.0 0.8 0.9 0.3 0.4 0.5 0.6 0.7 0.2 10 20 30 40 50 60 70 80 90 100 t a = +125 c pv1 = 13.5v t a = +25 c t a = -40 c 0 0.1 1.2 out2 efficiency vs. load current max16922 toc03 load current (a) efficiency (%) 0.5 0.4 0.3 0.2 60 70 80 90 100 50 0.1 0.6 pv2 = 5v out2 = 2.7v t a = +125 c t a = +25 c supply current vs. temperature max16922 toc04 temperature (c) supply current (ma) 110 95 -25 -10 5 35 50 65 20 80 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.0 -40 125 no load pwm = gnd normalized out1 voltage vs. load current max16922 toc05 i pv1 (a) normalized out1 voltage (%) 1.1 1.0 0.1 0.2 0.3 0.5 0.6 0.7 0.8 0.4 0.9 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 1.2 out1 voltage vs. v pv1 max16922 toc06 v pv1 (v) out1 voltage (v) 15 12 9 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 4.80 618 i out1 = 1a typical operating characteristics (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = +25?, unless otherwise specified.) max16922 toc07 power-up enable turning on en 10v/div out1 5v/div out3 2v/div out2 2v/div out4 1v/div 1ms/div power-up/down at thermal shutdown reset 5v/div out1 5v/div out2 2v/div out3 2v/div out4 1v/div 2ms/div max16922 toc08
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = +25?, unless otherwise specified.) switching frequency vs. load current max16922 toc09 load current (ma) switching frequency (mhz) 1000 800 600 400 200 0.4 0.8 1.2 1.6 2.0 0 0 1200 dropout voltage vs. load current max16922 toc10 load current (a) dropout voltage (v) 1.1 1.0 0.8 0.9 0.2 0.3 0.4 0.5 0.6 0.7 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 0 1.2 out2 out1 out3 out1 dropout voltage vs. temperature max16922 toc11 temperature ( c) dropout voltage (v) 110 95 80 65 50 35 20 5 -10 -25 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.7 -40 125 i out1 = 1.2a out2 dropout voltage vs. temperature max16922 toc12 temperature ( c) dropout voltage (v) 110 125 95 80 65 50 35 20 5 -10 -25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 -40 i out2 = 600ma out1 load transition i out1 500ma/div v out1 ac-coupled 50mv/div 20ms/div max16922 toc13 out2 load transient i out2 200ma/div v out2 ac-coupled 20mv/div 20ms/div max16922 toc14 out1 line transient 4ms/div max16922 toc15 pv1 5v/div out1 ac-coupled 20mv/div
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset _______________________________________________________________________________________ 7 switching frequency vs. temperature max16922 toc16 temperature ( c ) switching frequency (mhz) 110 95 65 80 -10 520 35 50 -25 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 2.30 pwm = out1 2.10 -40 125 power-supply rejection ratio vs . frequency max16922 toc17 frequency (hz) psrr (db) 10k 1k 100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 10 100k out3 out4 load current = 100ma 100mv p-p ripple out3 output-noise density vs. frequency max16922 toc18 frequency (hz) output-noise density (nv/ hz) 10k 1k 100 400 800 1200 1600 2000 2400 2800 3200 3600 4000 0 10 100k r l = 100 out4 output-noise density vs. frequency max16922 toc19 frequency (hz) output-noise density (nv/ hz) 10k 1k 100 200 400 600 800 1000 1200 1400 1600 1800 2000 0 10 100k r l = 100 typical operating characteristics (continued) (v pv1 = 13.5v, v pv2 = v pv3 = v out1 , v pv4 = v out2 ; t a = +25?, unless otherwise specified.)
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 8 _______________________________________________________________________________________ functional diagram en pwm en reset gnd1 out3 pv4 out4 en pv3 ep en pgnd2 lx2 lx1 pv2 pv1 outs2 outs1 bst lsup pwm gnd2 step-down pwm out2 1.0v to 3.9v 600ma step-down pwm out1 3.0v to 5.5v 1.2a linear regulator por generation ldo reg 1: 300ma 1.0v to 4.15v 1.0v to 4.15v mode select 10 f 2.2 h 4.7 h 4.7 f 4.7 f 1 f v out2 10 f v out1 v pv1 v out1 20k 100k 4.7 f 4.7 f 4.7 f 4.7 f en ldo reg 2: 300ma v out1 v out2 v out4 max16922
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset _______________________________________________________________________________________ 9 pin description pin tqfn tssop name function 1 3 bst bootstrap capacitor input. connect a 0.1? ceramic capacitor from bst to lx1. 2 4 pv1 out1 supply input. connect a 4.7? or larger ceramic capacitor from pv1 to pgnd. 3 5 lx1 ind uctor c onnecti on for ou t1. c onnect a 4.7? i nd uctor b etw een lx 1 and ou ts 1, and a s chottky d i od e b etw een lx 1 ( cathod e) and the p ow er - g r ound p l ane ( anod e) as show n i n the functi onal d i ag r am . 4 6 gnd3 ground. connect gnd, gnd1, gnd2, and gnd3 together. 5 7 outs1 out1 voltage-sensing input. connect outs1 directly to the out1 output voltage and bypass to power-ground plane with a minimum total capacitance of 15?. the total capacitance can include input bypass capacitors cascaded from out1, discharged by a 70 resistance between outs1 and gnd3 when disabled. 68pwm pwm control input. connect pwm to outs1 to force lx2 to switch every cycle. connect pwm to high for forced-pwm operation on out2. connect low for auto-pwm operation to improve efficiency at light loads. 7 9 gnd ground. connect gnd, gnd1, gnd2, and gnd3 together. pin configurations max16922 ep ep 11 12 13 14 15 5 4 3 2 1 pv2 pv3 out3 gnd2 out4 outs1 gnd3 lx1 pv1 bst 6 7 8 9 10 20 + 19 18 17 16 en gnd1 reset lsup pv4 pwm gnd outs2 pgnd2 lx2 tqfn top view max16922 16 17 18 19 20 5 4 3 2 1 + gnd2 out4 pv4 lsup lx1 pv1 bst en gnd1 11 12 13 14 15 10 9 8 7 6 pgnd2 lx2 pv2 pv3 out3 outs2 gnd pwm outs1 gnd3 tssop reset top view
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 10 ______________________________________________________________________________________ pin description (continued) pin tqfn tssop name function 8 10 outs2 out2 voltage sense input. connect outs2 directly to the out2 output voltage and bypass to pgnd2 with a minimum total capacitance of 10?. the total capacitance can include input bypass capacitors cascaded from out2, discharged by a 70 resistance between outs2 and pgnd2 when disabled. 9 11 pgnd2 power ground for buck 2. connect pgnd2 and gnd_ together near the device. 10 12 lx2 inductor connection for out2. connect a 2.2? inductor between lx2 and out2 as shown in the functional diagram . 11 13 pv2 out2 supply input. connect a 4.7? or larger ceramic capacitor from pv2 to ground. 12 14 pv3 linear-regulator power input for out3. bypass pv3 to gnd with a minimum 2.2? ceramic capacitor. 13 15 out3 linear-regulator 1 output. bypass out3 to gnd with a minimum 2.2? ceramic capacitor internally discharged by a 1k resistance when disabled. 14 16 gnd2 ground. connect gnd, gnd1, gnd2, and gnd3 together. 15 17 out4 linear-regulator 2 output. bypass out4 to gnd with a minimum 2.2? ceramic capacitor. internally discharged by a 1k resistance when disabled. 16 18 pv4 linear-regulator power input for out4. bypass pv4 to gnd with a minimum 2.2? ceramic capacitor. 17 19 lsup 5v logic supply to provide power to internal circuitry. bypass lsup to gnd1 with a 1? ceramic capacitor. 18 20 reset open-drain reset output for the input monitoring out1 and out2. external pullup required. 19 1 gnd1 ground. connect gnd, gnd1, gnd2, and gnd3 together. 20 2 en active-high enable input. connect en to pv1 or a logic-high voltage to turn on all regulators. pull en input low to place the regulators in shutdown. ep exposed pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to pgnd2 and gnd_. the exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the device.
max16922 detailed description the max16922 pmic is designed for medium power level automotive applications requiring multiple sup- plies in a small footprint. as shown in the typical applications circuit , the max16922 integrates one high-voltage power supply and three low-voltage cas- caded power supplies. out1 and out2 are step-down dc-dc converters, and out3 and out4 are linear reg- ulators. the device also includes a reset output ( reset ) and a high-voltage compatible enable input (en). the operating input voltage range is from 3.5v to 28v and tolerant of transient voltages up to 45v. out1 step-down dc-dc regulator step-down regulator architecture out1 is a high-input voltage, high-efficiency 2.2mhz pwm current-mode step-down dc-dc converter that delivers up to 1.2a. out1 has an internal high-side n- channel switch and uses a low forward-drop free- wheeling diode for rectification. under normal operating conditions, out1 is fixed frequency to pre- vent unwanted am radio interference. however, under light loads and high-input voltage, the step-down regu- lator skips cycles to maintain regulation. the output voltage is factory selectable from 3.0v to 5.5v in 50mv increments. soft-start when initially powered up or enabled with en, the out1 step-down regulator soft-starts by gradually ramping up the output voltage for approximately 2.2ms. this reduces inrush current during startup. during soft- start the full output current is available. before a soft- start sequence begins, the outputs of both dc-dc regulators discharge below 1.25v through an internal resistor. see the startup waveforms in the typical operating characteristics section. current limit the max16922 limits the peak inductor current sourced by the n-channel mosfet. when the peak current limit is reached, the internal n-channel mosfet turns off for the remainder of the cycle. if the current limit is exceeded for 16 consecutive cycles and the output voltage is less than 1.25v, the n-channel mos- fet is turned off for 256 clock cycles to allow the inductor current to discharge and then initiate a soft- start sequence for all four outputs. dropout the high-voltage, step-down converter (out1) of the max16922 is designed to operate near 100% duty- cycle. when the input voltage is close to the output voltage, the device tries to maintain the high-side switch on with 100% duty cycle. however, to maintain proper gate charge, the high-side switch must be turned off periodically so the lx pin can go to ground and charge the bst capacitor. as the input voltage approaches the output voltage, the effective duty cycle of the n-channel mosfet approaches 94%. every 4th cycle is limited to a maximum duty cycle of 75% (recharge period is approximately 112ns) while the remaining cycles can go to 100% duty cycle. as a result, when the max16922 is in dropout, the switching frequency is reduced by a factor of 4. during dropout conditions under light load, the load current may not be sufficient to enable the lx pin to reach ground during the recharge period. to ensure the lx pin is pulled to ground and proper bst capaci- tor recharge occurs, an internal load is applied to outs1 when pv1 falls below approximately 6.5v. this load is approximately 70 and is connected between outs1 and gnd3 through an internal switch. out2 step-down dc-dc regulator step-down regulator architecture out2 is a low-input voltage, high-efficiency 2.2mhz pwm current-mode step-down dc-dc converter that outputs up to 600ma. out2 has an internal high-side p-channel switch, and low-side n-channel switch for synchronous rectification. the dc-dc regulator sup- ports auto-pwm operation so that under light loads the device automatically enters high-efficiency skip mode. the auto-pwm mode can be disabled by connecting the pwm input to outs1. the output voltage is factory selectable from 1.0v to 3.9v in 50mv increments. soft-start out2 enters soft-start when out1 finishes its soft-start sequence to prevent high startup current from exceed- ing the maximum capability of out1. the step-down regulator executes a soft-start by gradually ramping up the output voltage for approximately 1.5ms. this reduces inrush current during startup. during soft-start, the full output current is available. the soft-start sequence on out2 begins after the soft-start sequence is completed on out1. see the startup waveforms in the typical operating characteristics section. 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset ______________________________________________________________________________________ 11
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 12 ______________________________________________________________________________________ current limit the max16922 limits the peak inductor current sourced by the p-channel mosfet. when the peak current limit is reached, the internal p-channel mosfet turns off for the remainder of the cycle. if the current limit is exceed- ed for 16 consecutive cycles, and the output voltage is less than 1.25v, the p-channel mosfet is turned off and enters output discharge mode for 256 clock cycles, allowing the inductor current and output voltage to discharge. once completed, a soft-start sequence is initiated on out2. dropout as the input voltage approaches the output voltage, the duty cycle of the p-channel mosfet reaches 100%. in this state, the p-channel mosfet is turned on constant- ly (not switching), and the dropout voltage is the volt- age drop due to the output current across the on-resistance of the internal p-channel mosfet (r pch ) and the inductor? dc resistance (r l ): v do = i load (r pch + r l ) pwm the max16922 operates in either auto-pwm or forced- pwm modes. at light load, auto-pwm switches only as needed to supply the load to improve light-load efficiency of the step-down converter. at higher load currents (~160ma), the step-down converter transitions to fixed 2.2mhz switching frequency. forced pwm always oper- ates with a constant 2.2mhz switching frequency regard- less of the load. connect pwm high for forced-pwm applications or low for auto-pwm applications. ldo linear regulators the max16922 contains two low-dropout linear regula- tors (ldos), out3 and out4. the ldo output voltages are factory preset, and each ldo supplies loads up to 300ma. the ldos include an internal reference, error amplifier, p-channel pass transistor, and internal volt- age-dividers. each error amplifier compares the refer- ence voltage to the output voltage (divided by the internal voltage-divider) and amplifies the difference. if the divided feedback voltage is lower than the refer- ence voltage, the pass-transistor gate is pulled lower, allowing more current to pass to the outputs and increasing the output voltage. if the divided feedback voltage is too high, the pass-transistor gate is pulled up, allowing less current to pass to the output. each output voltage is factory selectable from 1.0v to 4.15v in 50mv increments. if not using one of the ldo outputs, then tie the associated input power pin (pv_) to ground. input supply and undervoltage lockout an undervoltage-lockout circuit turns off the ldo regulators when the input supply voltage is too low to guarantee proper operation. when pv3 falls below 1.25v (typ), out3 powers down. when pv4 falls below 1.5v (typ), out4 powers down. soft-start out3 enters soft-start when pv3 exceeds 1.25v, and out4 enters soft-start when pv4 exceeds 1.5v. this staggers the surge current during startup to prevent excess current draw from out1 or out2 that could trigger an overcurrent shutdown. the soft-start time for each ldo is 0.1ms (typ). see the startup waveforms in the typical operating characteristics section. current limit the out3 and out4 output current is limited to 450ma (typ). if the output current exceeds the current limit, the corresponding ldo output voltage drops out of regula- tion. excess power dissipation in the device can cause the device to turn off due to thermal shutdown. dropout the dropout voltage for the linear regulators is 320mv (max) at 250ma load. to avoid dropout, make sure the input supply voltage corresponding to out3 and out4 is greater than the corresponding output voltage plus the dropout voltage based on the application output current requirements. lsup linear regulator lsup is the output of a 5v linear regulator that powers max16922 internal circuitry. lsup is internally powered from pv1 and automatically powers up when en is high and pv1 exceeds approximately 3.7v. lsup automati- cally powers down when en is taken low. bypass lsup to gnd with a 1? ceramic capacitor. lsup remains on even during a thermal fault. thermal-overload protection thermal-overload protection limits the total power dissi- pation in the max16922. thermal-protection circuits monitor the die temperature. if the die temperature exceeds +175?, the device shuts down, allowing it to cool. once the device has cooled by 15?, the device is enabled again. this results in a pulsed output during continuous thermal-overload conditions. the thermal- overload protection protects the max16922 in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junction temperature of +150?. see the thermal considerations section for more information.
max16922 applications information power-on sequence when the en input is pulled high and pv1 is greater than 3.7v (typ), the 5v lsup linear regulator turns on. once lsup exceeds 2.5v, the internal reference and bias are enabled. when the internal bias has stabilized out1, soft-start is initiated. after completion of soft-start on out1 (2.8ms typ), out2 soft-start is initiated. out3 soft-start is enabled when pv3 is greater than or equal to 1.25v (typ), and out4 soft-start is enabled when pv4 is greater than or equal to 1.5v (typ). care must be taken when driving the en pin. digital input signals deliver a fast edge that is properly detect- ed by the max16922. if driving the en pin with an ana- log voltage that has a slew rate of less than 1v/ms or a voltage-divider from pv1, then the input voltage on pv1 must always be less than 6v when the voltage at en is near the turn-off threshold of 1.6v. if this cannot be guaranteed, then a 1k resistor or 5.6v zener diode must be placed in parallel with the lsup output capaci- tor to prevent possible damage to the device. power-down and restart sequence the max16922 can be shut down by thermal shut- down, enable low (en), lsup regulator undervoltage, or when pv1 falls below 3.0v (typ). when a shutdown occurs, all outputs discharge through an internal resis- tor connected between each output and ground. when enable is high, the die temperature is okay, the lsup linear regulator is greater than 2.5v (typ), and out1 is less than 1.25v (typ); a complete soft-start power-on sequence is reinitiated. inductor selection the out1 step-down converter operates with a 4.7? inductor and the out2 step-down converter operates with a 2.2? inductor. the inductor? dc current rating must be high enough to account for peak ripple current and load transients. the step-down converter? archi- tecture has minimal current overshoot during startup and load transients. in most cases, an inductor capable of 1.3 times the maximum load current is acceptable. for optimum performance choose an inductor with dc- series resistance in the 50m to 150m range. for higher efficiency at heavy loads (above 400ma) and minimal load regulation, the inductor resistance should be kept as small as possible. for light-load applications (up to 200ma), higher resistance is acceptable with very little impact on performance. typical applications circuit max16922 ep pv1 en 4.7 f 220 f 0.1 f 1 f 0.1 f 10 f pv3 pwm 4.7 f v out1 out3 gnd1 gnd3 4.7 f pv4 outs1 4.7 f v out2 v out1 out4 gnd2 20k reset gnd 4.7 f lsup 4.7 h lx1 v out1 bst pv2 10 f pgnd2 2.2 h lx2 v out2 outs2 4.7 f vbat 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset ______________________________________________________________________________________ 13
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 14 ______________________________________________________________________________________ capacitor selection input capacitors the input capacitor, cin1, reduces the current peaks drawn from the supply and reduces switching noise in the max16922. the impedance of cin1 at the switch- ing frequency should be kept very low. ceramic capac- itors with x5r or x7r dielectrics are recommended due to their small size, low esr, and small temperature coefficients. use a 4.7? ceramic capacitor or an equivalent amount of multiple capacitors in parallel between pv1 and ground. connect cin1 as close to the device as possible to minimize the impact of pcb trace inductance. connect a minimum 4.7? ceramic capacitor between pv2 to ground, and a 2.2? ceramic capacitor between pv3 to ground and pv4 to ground. since pv2 is cas- caded from out1, the input capacitor connected to pv2 can be used as part of the total output capacitance for out1. step-down output capacitors the step-down output capacitors are required to keep the output-voltage ripple small and to ensure regulation loop stability. these capacitors must have low imped- ance at the switching frequency. surface-mount ceram- ic capacitors are recommended due to their small size and low esr. the capacitor should maintain its capacitance overtemperature and dc bias. ceramic capacitors with x5r or x7r temperature characteristics generally perform well. the output capacitance can be very low. place a minimum of 15? ceramic capaci- tance from outs1 to ground and a minimum of 10? from outs2 to ground. when the out2 output voltage selection is below 2.35v, the output capacitance should be increased to prevent instability. for optimum load- transient performance and very low output ripple, the output capacitance can be increased. the maximum output capacitance should not exceed 3.8mf for out1 and 2.0mf for out2. ldo output capacitors and stability connect a 4.7? ceramic capacitor between out3 and gnd, and a second 4.7? ceramic capacitor from out4 to gnd. when the input voltage of an ldo is greater than 2.35v, the output capacitor can be decreased to 2.2?. the equivalent series resistance (esr) of the ldo output capacitors affects stability and output noise. use output capacitors with an esr of 0.1 or less to ensure stable operation and optimum transient response. connect these capacitors as close as possible to the device to minimize pcb trace induc- tance. thermal considerations the maximum package power dissipation of the max16922 in the 20-pin thin qfn package is 2500mw. the power dissipated by the max16922 should not exceed this rating. the total device power dissipation is the sum of the power dissipation of the four regulators: p d = p d1 + p d2 + p d3 + p d4 estimate the out1 and out2 power dissipations as follows: where is the efficiency (see the typical operating characteristics section). calculate the out3 and out4 power dissipations as follows: p d3 = i out3 x (v pv3 ?v out3 ) p d4 = i out4 x (v pv4 ?v out4 ) the maximum junction temperature of the max16922 is +150?. the junction-to-case thermal resistance ( jc ) of the max16922 is 2.7?/w. when mounted on a single-layer pcb, the junction to ambient thermal resistance ( ja ) is approximately 48?/w. mounted on a multilayer pcb, ja is approxi- mately 32?/w. calculate the junction temperature of the max16922 as follows: t j = t a x p d x ja where t a is the maximum ambient temperature. make sure the calculated value of t j does not exceed the +150? maximum. pi v pi v dout out dout out 11 1 22 2 1 1 = ? = ?
max16922 pcb layout high-switching frequencies and relatively large peak currents make pcb layout a very important aspect of design. good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regula- tion errors. connect the input capacitors as close as possible to the pv_ and ground. connect the inductor and output capacitors as close as possible to the device and keep the traces short, direct, and wide to minimize the current loop area. the outs_ feedback connections are sensitive to inductor magnetic field interference so route these traces away from the inductors and noisy traces such as lx_. connect gnd_ and pgnd2 to the ground plane. connect the exposed paddle to the ground plane with multiple vias to help conduct heat away from the device. refer to the max16922 evaluation kit for a pcb layout example. 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset ______________________________________________________________________________________ 15 selector guide * other standard versions may be available. contact factory for availability. part number suffix* out1 voltage (v) out2 voltage (v) out3 voltage (v) out4 voltage (v) out1 reset threshold (%) reset timeout (ms) bst refresh load enable a 5.00 2.70 3.30 1.0 90 14.9 on b 5.00 1.20 1.80 3.3 90 14.9 on c 5.00 3.30 1.20 3.0 90 14.9 on d 3.6 1.2 3.3 3.3 90 14.9 off e 5.00 3.30 2.50 1.80 90 14.9 on f 5.00 1.20 3.15 3.00 90 14.9 on g 3.30 off 2.80 1.80 90 14.9 on h 3.30 1.20 2.50 1.80 90 14.9 off i 3.30 1.20 2.85 1.80 90 14.9 off j 3.80 3.30 2.50 1.20 90 14.9 off k 3.30 2.20 1.60 1.80 90 14.9 on lead free aec q100 qualified output voltages reset threshold, reset timeout -40 c to +125 c operation, tqfn, 20 pins max16922 atp x /v + lead free aec q100 qualified output voltages reset threshold, reset timeout -40 c to +125 c operation, tssop, 20 pins max16922 aup x /v +
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset 16 ______________________________________________________________________________________ chip information process: bicmos package type package code outline no. land pattern no. 20 tqfn-ep t2055+4 21-0140 90-0009 20 tssop-ep u20e+1 21-0108 90-0114 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status.
max16922 2.2mhz, dual, step-down dc-dc converters, dual ldos, and reset maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 5/10 updated absolute maximum ratings , electrical characteristics , typical operating characteristics , dropout , and power-on sequence sections 1, 2, 4, 6, 11, 13 2 10/10 added a new voltage trim option (i) to the selector guide 15 3 11/10 added a new voltage trim option (j) to the selector guide 15 4 4/11 added a new voltage trim option (k) to the selector guide 15 5 1/12 updated the functional diagram to eliminate the pwm signal on out1 and changed pv2 polarized capacitor to an unpolarized capacitor 8

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